1. Field of the Invention
The present invention relates to the controllable oscillators, and more particularly, regulation of a supply voltage for a controllable oscillator of a frequently synthesizer utilized in data detection circuits such as, for example, data detection circuits used with optical data disks.
2. Description of Related Art
In many data detection circuits an electrical signal is received from a data storage media, such as a CD-ROM, DVD, or other optical disk, magnetic hard disk, magnetic tape etc. In the case of optical disks, the electrical signal is generated from light that is reflected off an optical disk and converted to electrical pulses. The electrical pulses may then be transmitted to a data detection circuit for further signal processing to recover the data in a useable form. Data detection circuits may also be combined with circuitry for write operations. For example, circuitry for both read and write operations may be combined read/write channel circuits utilized with magnetic hard disks . In contrast, some optical disks are utilized in read only systems and thus the data detection circuit need not be combined with write circuitry. In general both read only and read/write data detection circuits may also include servo circuitry.
No matter what type of data storage media or data detection circuitry is utilized, a frequency synthesizer is often utilized to generate a clock signal for various circuit elements within the data detection or data write circuitry. For example, the continuous electrical pulse from an optical disk is generally converted into a discrete sample sequence by sampling the electrical pulses with an analog to digital converter (ADC) which may be clocked by the frequency synthesizer. Typically, the frequency synthesizer includes a phase locked loop (PLL). As shown in FIG. 1, a frequency synthesizer 1000 may be a phase locked loop (PLL) which may include a current controlled oscillator (ICO) 1013 and a reference clock input signal 1001. The phase locking loop is completed by feeding back the output of the oscillator to a phase/frequency detector which also receives the reference clock signal. More particularly, the reference clock 1001 is provided to a divider circuit 1003 which divides the reference clock signal by a value of N. The output of the divider 1003 is provided as one input to the phase/frequency detector 1005. The output of the phase/frequency detector is provided to a charge pump 1007 which in turn provides an output to a loop filter 1009. The voltage output of the loop filter 1009 is provided to transconductance stage 1011 which converts the voltage output of the loop filter to a current output. The transconductance stage 1011 has an output which is provided to the current controlled oscillator 1013. The current controlled oscillator may receive a voltage supply 1015. The output 1017 of the current controlled oscillator 1013 is provided as an output clock and also utilized in a feedback loop which is provided to the divider 1021 which divides the output 1017 by M. The output 1023 of the divider 1021 is then provided as the second input to the phase/frequency detector 1005. The M and N values may be called the PLL loop divisors since the output frequency at the PLL output 1017 is F.sub.S, and is given by EQU F=(M/N)F.sub.REF
where F.sub.REF is the reference clock frequency which may be typically provided from a crystal oscillator.
A frequency synthesizer such as shown in FIG. 1 is often sensitive to phase noise and jitter introduced at the current controlled oscillator. One factor which impacts the phase noise and jitter of the current controlled oscillator is the noise of the voltage supply 1015. Noise in the voltage supply will change the oscillation rate of the current controlled oscillator and inject phase noise in the phase locked loop output. In order to limit the impact of voltage supply noise, voltage regulators have been added between the voltage supply and the current controlled oscillator. For example, as shown in FIG. 1A, a voltage regulator circuit 1025 and capacitor 1029 may be coupled to the power supply input node 1027 of the current controlled oscillator 1013. However, it has been desirable to obtain improved voltage regulation over that obtained by use of a voltage regulator. In particular, it has been noted that the current demands drawn by the oscillator from the power supply may vary greatly and these large current demands tend to degrade the regulation performance of the voltage regulator which in turns degrades the performance of the current controlled oscillator. Thus, it would be desirable to provide an improved frequency synthesizer having an improved voltage regulation for the current controlled oscillator to improve noise and frequency jitter performance. Furthermore, it would be desirable to obtain such improved performance while utilizing a less complex voltage regulator.